Conventionally, among liquid crystal display devices, there has been a memory-type liquid crystal display device including memory-containing pixels (hereinafter referred to as “pixel memories”) and having a memory function that allows retention of image data. In such a liquid crystal display device, image data written to the pixels is retained by refreshing it while reversing its polarity, so that a still image can be displayed. During a normal operation (normal mode) in which the memory function is not used, the pixels are rewritten to new image data for each frame through the data signal lines. Meanwhile, during a memory operation (memory mode) in which the memory function is used, the image data is retained, so that it is not necessary to supply rewriting image data to the data signal lines.
Accordingly, during the memory operation, it becomes possible to suspend the operation of a circuit driving the scanning signal lines and the data signal lines and, therefore, to reduce power consumption. Moreover, a further reduction in power consumption can be achieved by reducing the number of times the large-capacity data signal lines are charged and discharged or dispensing with the transmission to a controller of image data corresponding to a period of the memory operation.
Therefore, such a memory-type liquid crystal display device is often used as a liquid crystal display device that displays images under strong demand for lower power consumption, as in the case of the standby screen of a cellular phone, for example.
FIG. 11 shows circuitry of a pixel memory (memory circuit MR100) extracted from a memory-type liquid crystal display device. The memory circuit MR100 is equivalent, for example, to the one disclosed in Patent Literature 1.
As shown in FIG. 11, the memory circuit MR100 includes a switch circuit SW100, a first data-retention section DS101, a data transfer section TS100, a second data-retention section DS102, and a refresh output control section RS100.
Further, the liquid crystal display device includes a substrate (not illustrated) having a matrix of such memory circuits MR100. The substrate is provided with a data transfer control line DTx, a gate line GLx, a High power line PHx, a Low power line PLx, a refresh output control line RCx, and an auxiliary capacitor line CSx for each row of the pixel matrix, and is provided with a source line SLx for each column of the pixel matrix. All these lines serve as wires to drive the memory circuits MR100.
The switch circuit SW100 is composed of a transistor N100, which is an N-channel TFT (thin-film transistor). The first data-retention section DS101 is composed of a capacitor Ca100. The data transfer section TS100 is composed of a transistor N101, which is an N-channel TFT. The second data-retention section DS102 is composed of a capacitor Cb100. The refresh output control section RS100 is composed of an inverter INV100 and a transistor N103, which is an N-channel TFT. The inverter INV100 is composed of a transistor P100, which is a P-channel TFT, and a transistor N102, which is an N-channel TFT.
It should be noted that such a field-effect transistor as the TFTs named above has two drain/source terminals one of which is called a first drain/source terminal and the other one of which is called a second drain/source terminal. However, the first drain/source terminal and the second drain/source terminal are called a drain terminal and a source terminal, respectively, or vice versa when they are definitely treated as such on the basis of the direction of flow of an electric current between them.
The transistor N100 has its gate terminal connected to the gate line GLx, its first drain/source terminal connected to the source line SLx, and its second drain/source terminal connected to a node PIX, which is an end of the capacitor Ca100, with the other end of the capacitor Ca100 connected to the auxiliary capacitor line CSx.
The transistor N101 has its gate terminal connected to the data transfer control line DTx, its first drain/source terminal connected to the node PIX, and its second drain/source terminal connected to a node MRY, which is an end of the capacitor Cb100, with the other end of the capacitor Cb100 connected to the auxiliary capacitor line CSx.
The inverter INV100 has its input terminal IP connected to the node MRY. The transistor P100 has its gate terminal connected to the input terminal IP of the inverter INV100, its source terminal connected to the High power line PHx, and its drain terminal connected to an output terminal OP of the inverter INV100. The transistor N102 has its gate terminal connected to the input terminal IP of the inverter INV100, its drain terminal connected to an output terminal OP of the inverter INV100, and its source terminal connected to the Low power line PLx.
The transistor N103 has its gate terminal connected to the refresh output control line RCx, its first drain/source terminal connected to the output terminal OP of the inverter INV100, and its second drain/source terminal connected to the node PIX.
Further, the liquid crystal display device includes a counter substrate (not illustrated) having a common electrode (counter electrode) COM, with the counter substrate being in such a position as to face the substrate having the memory circuits MR100. The substrate and the counter substrate are disposed in such a way that liquid crystals are sandwiched between them, and all these components constitute a liquid crystal panel. The node PIX of each of the memory circuits MR100 forms a liquid crystal capacitor C1c with the common electrode COM with liquid crystals sandwiched therebetween.
The memory operation (data-retention operation) of the memory circuit MR100 thus configured is explained below with reference to FIG. 12.
FIG. 12 is a timing chart showing waveforms of various signals during the memory mode in the memory circuit MR100.
During the memory mode, a driving circuit (not illustrated) applies a two-valued level potential, which consists of High (active-level) and Low (nonactive-level) levels of potential, to the data transfer control line DTx, the gate line GLx, and the refresh output control line RCx. The High and Low levels of potential may be set for each separate one of the lines.
Further, during the memory mode, the driving circuit (not illustrated) outputs a two-valued level data signal (also referred to as “two-valued data”), which consists of a High potential and a Low potential, to the source line SLx. A potential that is supplied through the High power line PHx is equal to the High potential of the two-valued level data signal, and a potential that is supplied through the Low power line PLx is equal to the Low potential of the two-valued level data signal. Furthermore, a potential that is supplied through the auxiliary capacitor line CSx may be constant or change at a predetermined timing. However, for simplicity of explanation, it is assumed here that the potential is constant.
During the memory mode, there are provided a total writing period T101 and a refresh period T102. The total writing period T101 is a period in which data to be retained in every memory circuit MR100 is written for each row. The total writing period T101 consists of a sequence of successive periods t101 and t102. Since, during the total writing period T101, line-sequential writing is performed on the memory circuits MR100, the period t101 for one row and that for another row are provided not to overlap. Therefore, the period t101 for one row and that for another row start at different timings. Further, the period t102 ends at the same timing in each row; that is, the total writing period T101 ends at the same timing in each row.
However, during the total writing period T101, the gate lines GL may be scanned at the same time in different rows, as long as timings (periods t101) of completion of scanning of the gate lines GL are shifted in sequence so that timings of completion of writing of data to the memory circuits MR101 vary from one row to another. For example, a method for scanning two gate lines GL every other gate line GL may be used. In the case of this method, while a timing of scanning for one row and that for another row may overlap, the timings of completion of writing of data vary.
The refresh period T102 is a period in which the data written to the memory circuits MR100 during the total writing period T101 is retained by refreshing it. The refresh period T102 has a sequence of successive periods t103 to t110. The refresh period T102 starts concurrently in each row.
During the period t101 in the total writing period T101, the gate line GLx has its potential raised to High. The potential of the data transfer control line DTx and that of the refresh output control line RCx are Low. This causes the transistor N100 to be in an ON state, whereby data potential (which is High here) supplied to the source line SLx is written to the node PIX.
Then, during the period t102, the gate line GLx has its potential dropped to Low. This causes the transistor N100 to be in an OFF state, whereby charge corresponding to the written data potential is retained in the capacitor Ca100.
It should be noted here that assuming that the memory circuit MR100 is composed solely of the capacitor Ca100 and the transistor N100, the node PIX becomes floating while the transistor N100 is in an OFF state. In an ideal state, the charge would be retained in the capacitor Ca100 so that the potential of the node PIX could be maintained at High.
In reality, however, there occurs an off-leakage current in the transistor N100; therefore, the charge in the capacitor Ca100 gradually leaks out of the memory circuit MR100. Because such a leakage of the charge in the capacitor Ca100 causes a change in the potential of the node PIX, a long-term leakage causes the potential of the node PIX to change to such an extent that the written data potential loses its original meaning.
Accordingly, during the refreshing period T102 that follows, the data transfer section TS100, the second data-retention section DS102, and the refresh output control section RS100 are made to function to refresh the potential of the node PIX so that the written data is not lost.
During the potential t103 in the refresh period T102, the data transfer control line DTx has its potential raised to High. The potential of the gate line GLx and the potential of the refresh output control line RCx are Low. This causes the transistor N101 to be in an ON state, whereby the capacitor Cb100 is connected in parallel to the capacitor Ca100 through the transistor N101. This causes a charge transfer between the capacitor Ca100 and the capacitor Cb100, whereby the potential of the node MRY becomes High.
It should be noted that the capacitor Ca100 has a larger capacitance value than the capacitor Cb100. Positive charge is transferred from the capacitor Ca100 to the capacitor Cb100 through the transistor N101 until the potential of the node PIX becomes equal to the potential of the node MRY. Although this causes the potential of the node PIX to be lower than the potential of the node PIX during the period t102 by a slight voltage ΔV1, the potential of the node PIX remains within a High potential range.
During the period t104 that follows, the data transfer control line DTx has its potential dropped to Low. This causes the transistor N101 to be in an OFF state, whereby the charge is retained in the capacitor Ca100 so that the potential of the node PIX is maintained at High and the charge is retained in the capacitor Cb100 so that the potential of the node MRY is maintained at High.
During the period t105, the refresh output control line RCx has its potential raised to High. This causes the transistor N103 to be in an ON state, whereby the output terminal OP of the inverter INV100 is connected to the node PIX. Since an inversion potential (which is Low here) of the potential of the node MRY is being outputted through the output terminal OP, the node PIX is charged by the inversion potential.
During the period t106, the refresh output control line RCx has its potential dropped to Low. This causes the transistor N103 to be in an OFF state, whereby the charge is retained in the capacitor Ca100 so that the potential of the node PIX is maintained at the inversion potential.
During the period t107, the data transfer control line DTx has its potential raised to High. This causes the transistor N101 to be in an ON state, whereby the capacitor Cb100 is connected in parallel to the capacitor Ca100 through the transistor N101. This causes a charge transfer between the capacitor Ca100 and the capacitor Cb100, whereby the potential of the node MRY becomes Low. It should be noted that positive charge is transferred from the capacitor Cb100 to the capacitor Ca100 through the transistor N101 until the potential of the node MRY becomes equal to the potential of the node PIX. Although this causes the potential of the node PIX to be lower than the potential of the node PIX during the period t106 by a slight voltage ΔV2, the potential of the node PIX remains within a Low potential range.
During the period t108, the data transfer control line DTx has its potential dropped to Low. This causes the transistor N101 to be in an OFF state, whereby the charge is retained in the capacitor Ca100 so that the potential of the node PIX is maintained at Low and the charge is retained in the capacitor Cb100 so that the potential of the node MRY is maintained at Low.
During the period t109, the refresh output control line RCx has its potential raised to High. This causes the transistor N101 to be in an ON state, whereby the output terminal OP of the inverter INV100 is connected to the node PIX. Since an inversion potential (which is High here) of the potential of the node MRY is outputted through the output terminal OP, the node PIX is charged by the inversion potential.
During the period t110, the refresh output control line RCx has its potential dropped to Low. This causes the transistor N103 to be in an OFF state, whereby the charge is retained in the capacitor Ca100 so that the potential of the node PIX is maintained at the inversion potential.
During the refresh period T102 that follows, the operation from the period t103 to the period t110 is repeated until a transition is made to the next total writing period T101 or to the normal mode. During the period t105 in the refresh period T102, the potential of the node PIX is refreshed to be an inversion potential, and during the period t109 in the refresh period T102, the potential of the node PIX is refreshed to be the potential that the node PIX had during writing. It should be noted that in a case where a Low data potential is written to the node PIX during the period t101 in the total writing period T101, the shape of potential of the node PIX looks like an inversion of that shown in FIG. 12.
In this way, the memory circuit MR100 allows data written during the total writing period T1 to be refreshed by a data inversion method during the refresh period T2. This makes it possible to curb the influence of a decrease in charge due to off-leakage. Further, depending on the timing when the data written to the node PIX is refreshed, i.e., on the timing when the polarity is reversed, the potential of the common electrode COM is inverted between High and Low. This makes it possible to refresh the screen while carrying out AC driving of the liquid crystal capacitor C1c. 
Incidentally, although, in the conventional memory-type liquid crystal display device, a reduction in power consumption is achieved through the memory mode, image noise (image distortion) sometimes occurs during at the time of a switch from one driving method to another since there exist a plurality of driving methods in accordance with a display mode.
For example, after a switch from the memory mode to the normal mode has been made, data in accordance with which a still image is displayed is retained in the pixel memories. As a result, when a switch from the normal mode to the memory mode is made next, image noise sometimes occurs because totally different data is displayed, albeit for a fleeting second, during a period up to completion of writing of new data to the pixel memories. In view of this, Patent Literature 2, for example, discloses a technique for retaining totally black/totally white data in every pixel memory at the end of a period in the memory mode during which a still image is displayed, i.e., for initializing the data-retention sections of the pixel memories. This prevents the previous data from being displayed when a switch from the normal mode to the memory mode is made next, thereby preventing image noise.